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In the new PPC 970 also AltiVec

If until a few hours ago there was still some subtle and faint doubt about the possibility that Apple might not even adopt IBM's PPC 970, after the presentation of the chip took place today in San Jos, this was also dispelled.

The details that Big Blue has made known all converge in one direction and point precisely to a product that is destined, if not exclusively, certainly in a very specific way to the Mac world.

The main of the signals confirms that the SIMD instructions (Single Instruction Multiple Data), a set of codes intended to accelerate particular vector calculations, are fully compatible with the Velocity Engine of the G4. Indeed, Peter Scandon, head of development, went even further, explicitly using the terminology "AltiVec", the way in which Motorola designates its instruction set.

The news, on the other hand, should not be surprising. At the end of 1999, at the time of the launch of the first G4 series, IBM had purchased from Motorola the possibility of using AltiVec in its future processors. At that time, the intention was precisely to produce G4 chips to come to the rescue of Motorola, entangled by the production system of the processor that forced Apple even to "downgrade" the speed of its machines.

IBM never produced any chips with AltiVec, a choice on which today it was forced to return since Apple's operating system founds (and in the future will increasingly merge) a large part of its competitiveness precisely on compatibility with Motorola's vector instructions.

To do this, Big Blue has chosen a much more complex, stimulated and full of performance potential by integrating AltiVec into an entirely new chip and not based on the architecture of the G4.

Scandon has confirmed, in fact, that the PPC 970 is in fact a reduced version of the Power4, the chip that IBM reserves for the most powerful workstations. It differs from it in having a single calculation unit and a longer instruction pipeline. This last detail means that the PPC 970 will have to have a higher clock speed to equate the real performance of the Power4.

Interesting is the bandwidth of the main bus supported by the PPC 970 which theoretically capable of reaching up to 900 MHz (currently the fastest G4 processor bus of only 167 MHz) with a nominal bandwidth of 7.2 GB per second.

The new processor has a 512kb second-level cache and no connectors for the third-level cache. Compared to Power4, however, the PPC 970 will have a more sophisticated circuitry of 0.13 microns (compared to 0.18 microns of the older brother), which will allow a lower consumption. The two processors share the use of the SOI system, which can also reduce consumption and heat production.

At 1.8 GHz, the threshold to which the PowerPC 970, consumer 1.3 volts and consumer 42 Watts should debut. At 1.2 GHz the consumption will be 1.1 volts for a consumption of only 19-Watts. In comparison, the 1 GHz G4 consumes 1.6 volts for 21.3-Watts. The PPC 970 will have 53 million transitors against 34 in the G4

At 1.8 GHz the PPC 970 will have the same performance as the Power4 at 1 GHz setting a threshold of 937 points in SPECint 2000.

IBM is now ready for some pre-series of the PPC 970, used for testing. Customers will have the first samples available in the first half of 2003. Series production will begin in the second half of next year.